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| Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated FEATURES * Repetitive Avalanche Rated * Fast switching * Stable off-state characteristics * High thermal cycling performance * Low thermal resistance * Extremely high dV/dt capability PHU2N50E QUICK REFERENCE DATA VDSS = 500 V ID = 2 A RDS(ON) 5 GENERAL DESCRIPTION N-channel, enhancement mode field-effect power transistor, intended for use in Compact Fluorescent Lamps (CFL) and low power ballasts. The PHU2N50E is compatible with self oscillating and IC driven circuits, including the UBA2021 ballast controller IC. Other applications include off line switched mode power supplies and D.C. to D.C. converters. The PHU2N50E is supplied in the SOT533 (I-PAK) leaded package. PINNING PIN DESCRIPTION ------------- --------------------------------1 gate 2 3 tab drain source drain SYMBOL d SOT533 g 1 2 3 MBK915 s Top view LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD dV/dt Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total dissipation Peak Diode Recovery voltage slope. (See fig. 19) Operating junction and storage temperature range CONDITIONS Tj = 25 C to 150C Tj = 25 C to 150C; RGS = 20 k Tmb = 25 C; VGS = 10 V Tmb = 100 C; VGS = 10 V Tmb = 25 C Tmb = 25 C Ids 2.0 A; dI/dt = 100 A/s; Vs = 8V; Tj < Tjmax MIN. - 55 MAX. 500 500 30 2 1.3 8 50 5.2 150 UNIT V V V A A A W V/ns C May 1999 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy CONDITIONS MIN. - PHU2N50E MAX. 82 UNIT mJ EAR IAS, IAR Unclamped inductive load, IAS = 1.26 A; tp = 0.2 ms; Tj prior to avalanche = 25C; VDD 50 V; RGS = 50 ; VGS = 10 V; refer to fig:17 Repetitive avalanche energy1 IAR = 2 A; tp = 2.5 s; Tj prior to avalanche = 25C; RGS = 50 ; VGS = 10 V; refer to fig:18 Repetitive and non-repetitive avalanche current - 3.3 2 mJ A THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. In free air TYP. MAX. UNIT 70 2.5 K/W K/W ELECTRICAL CHARACTERISTICS Tj = 25 C unless otherwise specified SYMBOL PARAMETER Drain-source breakdown voltage V(BR)DSS / Drain-source breakdown Tj voltage temperature coefficient Drain-source on resistance RDS(ON) VGS(TO) Gate threshold voltage gfs Forward transconductance Drain-source leakage current IDSS IGSS Qg(tot) Qgs Qgd td(on) tr td(off) tf Ld Ls Ciss Coss Crss V(BR)DSS CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 0.25 mA MIN. 500 2.0 0.5 TYP. MAX. UNIT 0.1 3.1 3.0 1.3 1 77 10 20 2 12 10 20 60 20 3.5 7.5 236 40 22 5 4.0 25 250 200 25 3 15 V %/K V S A A nA nC nC nC ns ns ns ns nH nH pF pF pF VGS = 10 V; ID = 1 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 1 A VDS = 500 V; VGS = 0 V VDS = 500 V; VGS = 0 V; Tj = 125 C Gate-source leakage current VGS = 30 V; VDS = 0 V Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 2 A; VDD = 400 V; VGS = 10 V VDD = 250 V; RD = 120 ; RG = 24 Measured from tab to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz 1 pulse width and repetition rate limited by Tj max. May 1999 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Tmb = 25C Tmb = 25C IS = 2 A; VGS = 0 V IS = 2 A; VGS = 0 V; dI/dt = 100 A/s MIN. - PHU2N50E TYP. MAX. UNIT 300 2.1 2 8 1.2 A A V ns C May 1999 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHU2N50E 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 10 Zth j-mb / (K/W) D= 0.5 0.2 0.1 0.05 0.1 0.02 0 T 0.01 t 0.1s 10ms P D tp D= tp T 1 0 20 40 60 80 100 Tmb / C 120 140 10us 1ms t/s Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb) ID% Normalised Current Derating Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T PHP2N50 120 110 100 90 80 70 60 50 40 30 20 10 0 6 5 4 3 2 ID, Drain current (Amps) Tj = 25 C 20 V 10 V 7V 6.5 V 6V 1 0 5.5 V VGS = 5 V 0 20 40 60 80 Tmb / C 100 120 140 0 5 10 15 20 VDS, Drain-Source voltage (Volts) 25 30 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 10 V PHP2N50 10 tp = 10 us Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS 10 Drain current, ID (Amps) Tmb = 25 C S RD 1 (ON )= VD D S/I Drain-Source on resistance, RDS(ON) (Ohms) 5V 5.5 V 6 V 6.5 V 7V PHP2N50 Tj = 25 C 8 100us 6 1 ms 10 V 4 VGS = 20 V DC 0.1 10 ms 100ms 2 0.01 10 100 Drain-source voltage, VDS (Volts) 1000 0 0 1 2 3 Drain current, ID (Amps) 4 5 Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS May 1999 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHU2N50E 6 5 4 3 2 Drain current, ID (A) VDS > ID x RDS(on)max PHP2N50 4 VGS(TO) / V max. 3 typ. min. 2 1 1 150 C 0 0 2 Tj = 25 C 0 4 6 Gate-source voltage, VGS (V) 8 10 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj Transconductance, gfs (S) VDS > ID x RDS(on)max 2 Tj = 25 C 1.5 150 C 1 PHP2N50 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS ID / A SUB-THRESHOLD CONDUCTION 2.5 1E-01 1E-02 1E-03 2% typ 98 % 1E-04 0.5 1E-05 0 1E-06 0 1 2 3 4 Drain current, ID (A) 5 6 0 1 2 VGS / V 3 4 Fig.8. Typical transconductance. gfs = f(ID); parameter Tj a Normalised RDS(ON) = f(Tj) Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS Capacitances, Ciss, Coss, Crss (pF) PHP2N50 1000 2 100 Ciss Coss 1 10 Crss 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 1 1 10 100 Drain-source voltage, VDS (V) 1000 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 1 A; VGS = 10 V Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz May 1999 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHU2N50E 20 Gate-Source voltage, VGS (Volts) ID = 2 A 300 V 200 V PHP2N50 10 Source-drain diode current, IF(A) VGS = 0 V PHP2N50 15 VDD = 400 V 8 150 C 6 Tj = 25 C 10 4 5 2 0 0 10 20 Gate charge, Qg (nC) 30 40 0 0 0.5 1 Source-Drain voltage, VSDS (V) 1.5 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS Switching times, td(on), tr, td(off), tf (ns) VDD = 250V RD = 120 Ohms Tj = 25 C PHP2N50 10 Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj 1000 Non-repetitive Avalanche current, IAS (A) Tj prior to avalanche = 25 C 100 td(off) 1 125 C 10 tr tf td(on) VDS 0.1 tp ID PHP2N50E 1E-05 1E-04 Avalanche time, tp (s) 1E-03 1E-02 1 0.01 1E-06 0 20 40 60 Gate resistance, RG (Ohms) 80 100 Fig.14. Typical switching times; td(on), tr, td(off), tf = f(RG) Fig.17. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tp); unclamped inductive load 1.15 1.1 1.05 1 0.95 0.9 Normalised Drain-source breakdown voltage V(BR)DSS @ Tj V(BR)DSS @ 25 C 10 Maximum Repetitive Avalanche Current, IAR (A) 1 Tj prior to avalanche = 25 C 0.1 125 C 0.01 PHP2N50E 0.001 1E-06 -50 0 50 Tj, Junction temperature (C) 100 150 0.85 -100 1E-05 1E-04 Avalanche time, tp (s) 1E-03 1E-02 Fig.15. Normalised drain-source breakdown voltage; V(BR)DSS/V(BR)DSS 25 C = f(Tj) Fig.18. Maximum permissible repetitive avalanche current (IAR) versus avalanche time (tp) May 1999 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHU2N50E dV/dt (V/ns) 7 6.5 6 5.5 5 4.5 4 3.5 3 0.4 0.8 1 Ids (A) 5 Fig.19. Peak body recovery voltage dV/dt. The dV/dt = f(IDS). The dI/dt is 100A/s. May 1999 7 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated MECHANICAL DATA Plastic single-ended package (Philips version of I-PAK); 3 leads (in-line) SOT533 PHU2N50E E E1 D1 mounting base D A1 A Q L 1 e1 e 2 b 3 wM c 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 2.38 2.22 A1 0.89 0.71 b c D 7.28 6.94 D1 1.06 0.96 E 6.73 6.47 E1 5.36 5.26 e e1 L 9.8 9.4 Q 1.00 1.10 0.89 0.56 0.71 0.46 4.57 2.285 OUTLINE VERSION SOT533 REFERENCES IEC JEDEC TO-251 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-02-18 Fig.20. SOT533 surface mounting package. Pin 2 connected to mounting base. May 1999 8 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated DEFINITIONS Data sheet status Objective specification Product specification Limiting values PHU2N50E This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. May 1999 9 Rev 1.000 |
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